yosys/techlibs at 5fa5dbbddab03af89e00426e21df9f30d020a94e - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 11:07:41 +02:00

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Clifford Wolf 5fa5dbbdda Rename "fine:" label to "map:" in "synth_ice40"

Signed-off-by: Clifford Wolf <[email protected]>

2018-12-16 16:36:19 +01:00

..

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

Leave only real black box cells

2018-12-02 11:57:50 +01:00

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

ecp5: Add 'fake' DCU parameters

2018-11-09 18:25:42 +00:00

Changes in GoWin synth commands and ALU primitive support

2018-12-03 20:08:35 -06:00

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

Rename "fine:" label to "map:" in "synth_ice40"

2018-12-16 16:36:19 +01:00

Changes in GoWin synth commands and ALU primitive support

2018-12-03 20:08:35 -06:00

Fix sf2 LUT interface

2018-10-31 15:36:53 +01:00

Add support for Xilinx PS7 block

2018-11-10 12:45:07 -08:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00