Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL ...

As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser

2020-04-27 09:44:24 -07:00

..

aiger

xaiger: add check for $__ABC9_DELAY model

2020-04-13 19:11:23 -07:00

blif

kernel: big fat patch to use more ID::*, otherwise ID(*)

2020-04-02 09:51:32 -07:00

btor

kernel: big fat patch to use more ID::*, otherwise ID(*)

2020-04-02 09:51:32 -07:00

cxxrtl

cxxrtl: keep the memory write queue sorted on insertion.

2020-04-22 20:53:12 +02:00

edif

Improve net priorities in EDIF back-end

2020-04-21 12:35:25 +02:00

firrtl

ast, rpc: record original name of $paramod\* as \hdlname attribute.

2020-04-18 03:47:28 +00:00

ilang

Preserve 'signed'-ness of a verilog wire through RTLIL

2020-04-27 09:44:24 -07:00

intersynth

Clean up pseudo-private member usage in backends/intersynth/intersynth.cc.

2020-04-01 06:32:09 +00:00

json

Preserve 'signed'-ness of a verilog wire through RTLIL

2020-04-27 09:44:24 -07:00

protobuf

Add aiger and protobuf backends binary support

2019-09-28 09:51:48 +02:00

simplec

kernel: big fat patch to use more ID::*, otherwise ID(*)

2020-04-02 09:51:32 -07:00

smt2

Merge pull request #1830 from boqwxp/qbfsat

2020-04-15 17:33:50 +02:00

smv

kernel: big fat patch to use more ID::*, otherwise ID(*)

2020-04-02 09:51:32 -07:00

spice

kernel: use more ID::*

2020-04-02 07:14:08 -07:00

table

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

verilog

write_verilog: fix precondition check.

2020-04-14 12:12:50 +00:00