mirror of https://github.com/YosysHQ/yosys.git
33 lines
792 B
Systemverilog
33 lines
792 B
Systemverilog
module memtest05(clk, addr, wdata, rdata, wen);
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input clk;
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input [1:0] addr;
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input [7:0] wdata;
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output reg [7:0] rdata;
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input [3:0] wen;
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reg [7:0] mem [0:3] = {8'h01, 8'h23, 8'h45, 8'h67};
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integer i;
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always @(posedge clk) begin
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for (i = 0; i < 4; i = i+1)
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if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
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rdata <= mem[addr];
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end
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always @(posedge clk) begin
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// not sure how to verify this one without SBY
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// or alternatively, how to replicate the problematic sub addressing without the read&write
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assume (wen == 0);
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assert (mem[0][7:4] == 4'h0);
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assert (mem[0][3:0] == 4'h1);
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assert (mem[1][7:4] == 4'h2);
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assert (mem[1][3:0] == 4'h3);
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assert (mem[2][7:4] == 4'h4);
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assert (mem[2][3:0] == 4'h5);
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assert (mem[3][7:4] == 4'h6);
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assert (mem[3][3:0] == 4'h7);
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end
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endmodule
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