luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 04:41:06 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
5ea2c6e6e56075b9d6402cf93d3e12da46707db5
yosys/tests/sim
T
History
Roland CoeurjolyandMiodrag Milanovic 5ea2c6e6e5 Assume x values for missing signal data in FST 
Co-authored-by: Miodrag Milanovic <[email protected]>
Co-authored-by: Roland Coeurjoly <[email protected]>
2024-10-02 12:08:48 +02:00
..
tb
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
.gitignore
Added test cases
2022-02-16 13:27:59 +01:00
adff.v
Added test cases
2022-02-16 13:27:59 +01:00
adffe.v
Added test cases
2022-02-16 13:27:59 +01:00
adlatch.v
Added test cases
2022-02-16 13:27:59 +01:00
aldff.v
Added test cases
2022-02-16 13:27:59 +01:00
aldffe.v
Added test cases
2022-02-16 13:27:59 +01:00
assume_x_first_step.ys
Assume x values for missing signal data in FST
2024-10-02 12:08:48 +02:00
dff.v
Added test cases
2022-02-16 13:27:59 +01:00
dffe.v
Added test cases
2022-02-16 13:27:59 +01:00
dffsr.v
Added test cases
2022-02-16 13:27:59 +01:00
dlatch.v
Added test cases
2022-02-16 13:27:59 +01:00
dlatchsr.v
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
run-test.sh
Replace GNU specific invocation of basename(1) with the equivalent
2022-10-23 11:02:18 +13:00
sdff.v
Added test cases
2022-02-16 13:27:59 +01:00
sdffce.v
Added test cases
2022-02-16 13:27:59 +01:00
sdffe.v
Added test cases
2022-02-16 13:27:59 +01:00
sim_adff.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_adffe.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_adlatch.ys
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
sim_aldff.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_aldffe.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dff.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dffe.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dffsr.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dlatch.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_dlatchsr.ys
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
sim_sdff.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_sdffce.ys
Added test cases
2022-02-16 13:27:59 +01:00
sim_sdffe.ys
Added test cases
2022-02-16 13:27:59 +01:00
simple_assign.v
Assume x values for missing signal data in FST
2024-10-02 12:08:48 +02:00
simple_assign.vcd
Assume x values for missing signal data in FST
2024-10-02 12:08:48 +02:00