whitequark 3bffd09d64 Merge pull request #2006 from jersey99/signed-in-rtlil-wire ... Preserve 'signed'-ness of a verilog wire through RTLIL		2020-06-04 11:23:06 +00:00
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aiger	aiger: -xaiger to return $_FF_ flops	2020-05-14 10:33:56 -07:00
ast	Merge pull request #2006 from jersey99/signed-in-rtlil-wire	2020-06-04 11:23:06 +00:00
blif	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
ilang	Merge pull request #2006 from jersey99/signed-in-rtlil-wire	2020-06-04 11:23:06 +00:00
json	frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire	2020-04-27 10:36:18 -07:00
liberty	kernel: big fat patch to use more ID::*, otherwise ID(*)	2020-04-02 09:51:32 -07:00
rpc	Add WASI platform support.	2020-04-30 18:56:25 +00:00
verific	Support asymmetric memories for verific frontend	2020-06-01 10:30:03 +02:00
verilog	Merge pull request #2033 from boqwxp/cleanup-verilog-lexer	2020-05-29 06:46:33 +00:00