Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
5e0339855fc1f83b98694ed37dd2f195c3d8f52c
yosys/techlibs
T
History
Keith Rothman 5e0339855f Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <[email protected]>
2019-04-09 09:01:53 -07:00
..
achronix
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
anlogic
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
common
Merge pull request #772 from whitequark/synth_lut
2019-01-02 15:44:57 +01:00
coolrunner2
Unify usage of noflatten among architectures
2019-01-04 11:37:25 +01:00
easic
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
ecp5
ecp5: Demote conflicting FF init values to a warning
2019-03-04 11:26:20 +00:00
gowin
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
greenpak4
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
ice40
Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes
2019-03-12 20:14:18 +01:00
intel
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
sf2
Add link to SF2 / igloo2 macro library guide
2019-03-07 09:08:26 -08:00
xilinx
Add additional cells sim models for core 7-series primatives.
2019-04-09 09:01:53 -07:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
Powered by Gitea Version: 1.27.2 Page: 106ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API