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yosys/backends
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Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
2021-12-12 19:56:50 +01:00
..
aiger
sta: very crude static timing analysis pass
2021-11-25 17:20:27 +01:00
blif
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
btor
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
cxxrtl
cxxrtl: preserve interior memory pointers across reset.
2021-12-11 16:40:06 +00:00
edif
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
firrtl
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
intersynth
Intersynth URL
2021-06-09 12:42:52 +02:00
json
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
protobuf
Fix protobuf backend build dependencies
2021-09-17 13:36:39 +10:00
rtlil
rtlil: Dump empty connections when whole module is selected.
2021-12-12 01:22:06 +01:00
simplec
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
smt2
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
smv
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
spice
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
table
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
verilog
Add clean_zerowidth pass, use it for Verilog output.
2021-12-12 19:56:50 +01:00