mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-03 11:18:31 +02:00
Jim Lawson
171c425cf9
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)