mirror of https://github.com/YosysHQ/yosys.git
14c03861b6
Refactor abc9 to use port attributes, not module attributes |
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|---|---|---|
| .. | ||
| tests | ||
| .gitignore | ||
| Makefile.inc | ||
| abc_hx.box | ||
| abc_hx.lut | ||
| abc_lp.box | ||
| abc_lp.lut | ||
| abc_u.box | ||
| abc_u.lut | ||
| arith_map.v | ||
| brams.txt | ||
| brams_init.py | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| ice40_braminit.cc | ||
| ice40_ffinit.cc | ||
| ice40_ffssr.cc | ||
| ice40_opt.cc | ||
| latches_map.v | ||
| synth_ice40.cc | ||