mirror of https://github.com/YosysHQ/yosys.git
8e97f34d31
Add simulation models, techmap, and dfflegalize rules for Gowin DL-series latch primitives. Latches use the same physical BEL as DFFs with REGMODE set to LATCH. All 12 variants are supported: DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE. |
||
|---|---|---|
| .. | ||
| anlogic | ||
| common | ||
| ecp5 | ||
| efinix | ||
| fabulous | ||
| gatemate | ||
| gowin | ||
| ice40 | ||
| intel_alm | ||
| machxo2 | ||
| microchip | ||
| nanoxplore | ||
| nexus | ||
| quicklogic | ||
| xilinx | ||
| run-test.sh | ||