yosys/techlibs/gowin
Justin Zaun 5cc76ceabb gowin: remove lib_whitebox from latch sim cells
Latches are sequential elements and don't need lib_whitebox.
2026-03-02 16:22:33 -10:00
..
Makefile.inc gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 2026-03-01 16:11:30 -10:00
adc.v Gowin. Fix GW5A ADCs. 2025-10-29 12:48:21 +10:00
arith_map.v gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
brams.txt Gowin. Implement byte enable. 2026-01-03 17:42:49 +10:00
brams_map.v gowin: Fix bram ADA byte enables 2026-02-22 09:00:37 +01:00
brams_map_gw5a.v gowin: Fix bram ADA byte enables 2026-02-22 09:00:37 +01:00
cells_latch.v gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 2026-03-01 16:11:30 -10:00
cells_map.v iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
cells_sim.v gowin: remove lib_whitebox from latch sim cells 2026-03-02 16:22:33 -10:00
cells_xtra.py Gowin. Fix GW5A ADCs. 2025-10-29 12:48:21 +10:00
cells_xtra_gw1n.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
cells_xtra_gw2a.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
cells_xtra_gw5a.v Add and use fix_mod.py 2026-01-28 07:45:58 +13:00
dsp_map.v gowin: format MULT instances 2026-02-12 13:35:49 +03:00
lutrams.txt gowin: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v gowin: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
synth_gowin.cc gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 2026-03-01 16:11:30 -10:00