Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 11:29:42 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
5c82c19b4b58dfa6a1e03195a81d4e9a23cd7848
yosys/tests/arch
T
History
Dan Ravensloft 3d149aff73 intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
..
anlogic
Simplify breaking tests/arch/*/fsm.ys tests
2020-03-20 11:25:17 -07:00
common
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
2020-02-06 16:52:51 +00:00
ecp5
tests: remove write_ilang
2020-04-20 15:42:29 -07:00
efinix
Simplify breaking tests/arch/*/fsm.ys tests
2020-03-20 11:25:17 -07:00
gowin
Add opt_lut_ins pass. (#1673)
2020-02-03 14:57:17 +01:00
ice40
test: ice40_dsp test to read +/ice40/cells_sim.v for default params
2020-04-22 16:35:35 -07:00
intel_alm
intel_alm: work around a Quartus ICE
2020-04-23 11:03:28 +02:00
xilinx
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
2020-04-22 17:50:30 -07:00
run-test.sh
tests: extend tests/arch/run-tests.sh for defines
2020-03-05 08:08:32 -08:00
Powered by Gitea Version: 1.27.2 Page: 83ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API