mirror of https://github.com/YosysHQ/yosys.git
296 lines
8.5 KiB
C++
296 lines
8.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2026 Akash Levy <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void merge_add_attributes(Cell *dst, const Cell *outer, const Cell *inner)
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{
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dst->attributes = outer->attributes;
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for (const auto &attr : inner->attributes)
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if (attr.first != ID::src && !dst->attributes.count(attr.first))
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dst->attributes[attr.first] = attr.second;
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std::string outer_src = outer->get_src_attribute();
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std::string inner_src = inner->get_src_attribute();
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if (outer_src.empty()) {
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if (!inner_src.empty())
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dst->set_src_attribute(inner_src);
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} else if (!inner_src.empty() && inner_src != outer_src) {
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dst->set_src_attribute(outer_src + "|" + inner_src);
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}
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}
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struct OptAddcinWorker
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{
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struct Leaf {
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SigSpec sig;
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bool is_signed;
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};
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struct Rewrite {
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Cell *outer;
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Cell *inner;
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Leaf a;
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Leaf b;
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SigSpec cin;
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SigSpec y;
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int width;
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};
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Module *module;
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SigMap sigmap;
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dict<SigSpec, Cell*> add_driver;
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pool<SigBit> tracked_output_bits;
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dict<SigBit, int> input_users;
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pool<Cell*> claimed;
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vector<Rewrite> rewrites;
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OptAddcinWorker(Module *module) : module(module), sigmap(module)
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{
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}
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void build_indexes()
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{
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for (auto cell : module->selected_cells()) {
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if (cell->type != ID($add))
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continue;
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SigSpec y = sigmap(cell->getPort(ID::Y));
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add_driver[y] = cell;
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for (auto bit : y)
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tracked_output_bits.insert(bit);
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}
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for (auto wire : module->wires()) {
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if (!wire->port_output)
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continue;
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for (auto bit : sigmap(wire))
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if (tracked_output_bits.count(bit))
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input_users[bit]++;
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}
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for (auto cell : module->cells()) {
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for (auto &conn : cell->connections()) {
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if (!cell->input(conn.first))
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continue;
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for (auto bit : sigmap(conn.second))
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if (tracked_output_bits.count(bit))
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input_users[bit]++;
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}
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}
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}
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Cell *driver_of(const SigSpec &sig)
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{
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auto it = add_driver.find(sig);
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return it == add_driver.end() ? nullptr : it->second;
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}
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bool has_single_use(const SigSpec &sig)
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{
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for (auto bit : sig) {
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auto it = input_users.find(bit);
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if (it == input_users.end() || it->second != 1)
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return false;
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}
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return true;
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}
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bool collect(Cell *outer)
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{
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if (claimed.count(outer) || outer->type != ID($add))
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return false;
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SigSpec outer_a = sigmap(outer->getPort(ID::A));
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SigSpec outer_b = sigmap(outer->getPort(ID::B));
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SigSpec outer_y = sigmap(outer->getPort(ID::Y));
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Cell *inner_a = driver_of(outer_a);
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Cell *inner_b = driver_of(outer_b);
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if ((inner_a != nullptr) == (inner_b != nullptr))
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return false;
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Cell *inner = inner_a ? inner_a : inner_b;
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if (inner == outer || claimed.count(inner) || inner->type != ID($add))
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return false;
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SigSpec inner_y = sigmap(inner->getPort(ID::Y));
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SigSpec inner_operand = inner_a ? outer_a : outer_b;
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if (inner_y != inner_operand)
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return false;
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int width = GetSize(outer_y);
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if (width == 0 || GetSize(inner_y) != width)
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return false;
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if (inner->getParam(ID::Y_WIDTH).as_int() != width)
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return false;
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if (outer->getParam(ID::Y_WIDTH).as_int() != width)
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return false;
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if (!has_single_use(inner_y))
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return false;
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vector<Leaf> leaves;
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leaves.push_back({sigmap(inner->getPort(ID::A)), inner->getParam(ID::A_SIGNED).as_bool()});
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leaves.push_back({sigmap(inner->getPort(ID::B)), inner->getParam(ID::B_SIGNED).as_bool()});
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if (inner_a)
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leaves.push_back({outer_b, outer->getParam(ID::B_SIGNED).as_bool()});
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else
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leaves.push_back({outer_a, outer->getParam(ID::A_SIGNED).as_bool()});
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int cin_index = -1;
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for (int i = 0; i < GetSize(leaves); i++) {
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if (GetSize(leaves[i].sig) > width)
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return false;
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if (GetSize(leaves[i].sig) == 1 && !leaves[i].is_signed) {
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if (cin_index != -1)
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return false;
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cin_index = i;
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}
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}
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if (cin_index == -1)
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return false;
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vector<Leaf> operands;
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for (int i = 0; i < GetSize(leaves); i++) {
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if (i == cin_index)
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continue;
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operands.push_back(leaves[i]);
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}
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log_assert(GetSize(operands) == 2);
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claimed.insert(outer);
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claimed.insert(inner);
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rewrites.push_back({outer, inner, operands[0], operands[1], leaves[cin_index].sig, outer_y, width});
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return true;
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}
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SigSpec extend_leaf(const Leaf &leaf, int width)
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{
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SigSpec sig = leaf.sig;
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sig.extend_u0(width, leaf.is_signed);
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return sig;
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}
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void apply(const Rewrite &rewrite)
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{
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Cell *cell = rewrite.outer;
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SigSpec a = extend_leaf(rewrite.a, rewrite.width);
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SigSpec b = extend_leaf(rewrite.b, rewrite.width);
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SigSpec wide_a(State::S1);
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wide_a.append(a);
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SigSpec wide_b = rewrite.cin;
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wide_b.append(b);
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Wire *wide_y_wire = module->addWire(NEW_ID2_SUFFIX("addcin_y"), rewrite.width + 1);
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SigSpec wide_y(wide_y_wire);
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Cell *wide_add = module->addCell(NEW_ID2_SUFFIX("addcin"), ID($add));
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merge_add_attributes(wide_add, rewrite.outer, rewrite.inner);
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wide_add->setPort(ID::A, wide_a);
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wide_add->setPort(ID::B, wide_b);
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wide_add->setPort(ID::Y, wide_y);
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wide_add->setParam(ID::A_SIGNED, false);
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wide_add->setParam(ID::B_SIGNED, false);
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wide_add->fixup_parameters();
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module->connect(rewrite.y, wide_y.extract(1, rewrite.width));
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module->remove(rewrite.outer);
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module->remove(rewrite.inner);
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}
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int run()
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{
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build_indexes();
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vector<Cell*> cells;
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for (auto cell : module->selected_cells())
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cells.push_back(cell);
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for (auto cell : cells)
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collect(cell);
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for (auto &rewrite : rewrites)
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apply(rewrite);
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return GetSize(rewrites);
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}
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};
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struct OptAddcinPass : public Pass {
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OptAddcinPass() : Pass("opt_addcin", "rewrite add-with-carry-in patterns as widened adders") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_addcin [selection]\n");
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log("\n");
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log("This pass rewrites a conservative two-$add, three-leaf carry-in pattern\n");
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log("into a single widened $add:\n");
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log("\n");
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log(" (A + B) + CI -> ({A_ext, 1'b1} + {B_ext, CI})[WIDTH:1]\n");
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log("\n");
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log("Only one leaf may be a one-bit unsigned carry input. The other two leaves\n");
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log("are explicitly sign- or zero-extended to the shared add width before the\n");
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log("widened add is emitted. The pass rejects $sub/$alu patterns, mismatched\n");
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log("intermediate/final widths, multi-bit carry operands, signed carry operands,\n");
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log("and intermediate sums with fanout outside the final add.\n");
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log("\n");
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log("This pass is not invoked by the default 'opt' or 'peepopt' scripts. It is\n");
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log("intended for flows that want to map carry-in adds onto adders without an\n");
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log("explicit carry input. Run add-chain timing transforms such as\n");
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log("'opt_balance_tree -arith' or 'opt_parallel_prefix -arith' before this pass,\n");
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log("then run 'alumacc' or technology mapping afterwards.\n");
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log("\n");
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log("Runtime is linear in the number of module connections plus the total width\n");
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log("of rewritten candidates. The implementation builds driver and input-use\n");
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log("indexes once per module and does not scan all cells per candidate.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing OPT_ADDCIN pass (carry-in add widening).\n");
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size_t argidx = 1;
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extra_args(args, argidx, design);
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int total = 0;
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for (auto module : design->selected_modules()) {
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OptAddcinWorker worker(module);
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int count = worker.run();
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total += count;
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if (count)
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log("Rewrote %d add-carry-in pattern%s in module %s.\n",
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count, count == 1 ? "" : "s", log_id(module));
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}
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if (total)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Rewrote %d add-carry-in pattern%s total.\n", total, total == 1 ? "" : "s");
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}
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} OptAddcinPass;
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PRIVATE_NAMESPACE_END
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