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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 02:23:09 +02:00
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5b6b3d01bf2fdfed181a30ab685f7bd8d4845a39
yosys/techlibs/intel
T
History
Richard Herveille 2893938355 Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneive
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
max10
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
Makefile.inc
synth_intel: Remove incomplete Arria 10 GX support.
2020-08-21 01:46:06 +02:00
synth_intel.cc
removed commented out code
2024-03-15 01:48:22 +01:00
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