yosys/techlibs/xilinx at 5ab59cd59ee90abc4b6991486854dbe4c3f4d0a4 - yosys - Gitea: Git with a cup of tea

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Eddie Hung 02973474df Remove extra newline

2019-06-03 20:04:47 -07:00

..

Improved xilinx "bram1" test

2015-04-09 17:12:12 +02:00

.gitignore

…

arith_map.v

Changes required for VPR place and route synth_xilinx.

2019-03-01 12:02:27 -08:00

brams_bb.v

…

brams_init.py

Squelch trailing whitespace, including meta-whitespace

2018-03-11 16:03:41 +01:00

brams_map.v

Revert BRAM WRITE_MODE changes.

2019-03-04 09:22:22 -08:00

brams.txt

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

cells_map.v

Rename cells_map.v to prevent clash with ff_map.v

2019-05-03 14:40:32 -07:00

cells_sim.v

Merge remote-tracking branch 'origin' into xc7srl

2019-04-20 10:41:43 -07:00

cells_xtra.sh

Merge remote-tracking branch 'origin' into xc7srl

2019-04-20 10:41:43 -07:00

cells_xtra.v

Merge remote-tracking branch 'origin' into xc7srl

2019-04-20 10:41:43 -07:00

drams_map.v

…

drams.txt

Add "min bits" and "min wports" to xilinx dram rules

2019-05-23 11:32:28 -07:00

ff_map.v

Move neg-pol to pos-pol mapping from ff_map to cells_map.v

2019-04-28 12:36:04 -07:00

lut_map.v

Changes required for VPR place and route synth_xilinx.

2019-03-01 12:02:27 -08:00

Makefile.inc

Changes required for VPR place and route synth_xilinx.

2019-03-01 12:02:27 -08:00

synth_xilinx.cc

Remove extra newline

2019-06-03 20:04:47 -07:00