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13 lines
345 B
Plaintext
13 lines
345 B
Plaintext
read_verilog <<EOT
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module top(input a, input b, output o);
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(* keep *) wire w = a & b;
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assign o = ~w;
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endmodule
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EOT
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hierarchy -check -top top
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proc; opt -fast; techmap
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abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
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select -assert-none t:$_AND_
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select -assert-min 1 t:NAND t:NOT t:NOR t:BUF %u
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