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19 lines
413 B
Plaintext
19 lines
413 B
Plaintext
read_verilog -icells -specify <<EOT
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(* abc9_box, blackbox *)
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module box1(input i, output o);
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specify
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(i => o) = 1;
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endspecify
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endmodule
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module top(input a, input b, output o);
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wire z;
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$_AND_ gate(.A(a), .B(b), .Y(o));
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box1 u_box(.i(a), .o(z));
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endmodule
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EOT
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hierarchy -check -top top
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abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
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select -assert-min 1 t:*
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