Clifford Wolf f9a307a50b namespace Yosys

2014-09-27 16:17:53 +02:00

..

example_mojo_counter

…

example_sim_counter

Fixed xilinx/example_sim_counter test bench

2013-11-24 17:55:46 +01:00

example_zed_counter

[EXAMPLES] Ported the mojo counter example to Zynq ZED board.

2013-10-27 21:48:39 +01:00

cells.v

Renamed $lut ports to follow A-Y naming scheme

2014-08-15 14:18:40 +02:00

Makefile.inc

Added "make PRETTY=1"

2014-07-24 17:15:01 +02:00

synth_xilinx.cc

namespace Yosys

2014-09-27 16:17:53 +02:00