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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 10:39:10 +02:00
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55dc5a4e4f7335741d2155dc0183ed4e26e8ddf8
yosys/tests/arch
T
History
Marcelina Kościelnicka 4a35f244aa quicklogic: Add .gitignore file for test outputs.
2021-03-23 17:35:00 +01:00
..
anlogic
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
common
intel_alm: Add multiply signedness to cells
2020-08-26 22:50:16 +02:00
ecp5
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
efinix
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
gowin
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
ice40
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
intel_alm
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
machxo2
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
2021-02-23 17:39:58 +01:00
nexus
nexus: DSP inference support
2020-11-20 08:45:55 +00:00
quicklogic
quicklogic: Add .gitignore file for test outputs.
2021-03-23 17:35:00 +01:00
xilinx
ast: Use better parameter serialization for paramod names.
2021-03-18 00:52:00 +01:00
run-test.sh
tests: extend tests/arch/run-tests.sh for defines
2020-03-05 08:08:32 -08:00
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