mirror of https://github.com/YosysHQ/yosys.git
35 lines
791 B
Plaintext
35 lines
791 B
Plaintext
# Ensure wreduce propagates width reductions across dependent cells.
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read_verilog <<EOT
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module top(input [7:0] a, input [7:0] b, input [3:0] c, output [3:0] y);
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wire [8:0] sum_full;
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wire [3:0] sum_trunc;
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assign sum_full = a + b;
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assign sum_trunc = sum_full[3:0];
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assign y = sum_trunc + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_expr
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opt_clean
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design -save gold
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wreduce
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opt_clean
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# After wreduce, the first add should be reduced from 9 bits to 4 bits
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select -assert-count 2 t:$add
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select -assert-count 0 t:$add r:Y_WIDTH=9 %i
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select -assert-count 2 t:$add r:Y_WIDTH=4 %i
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design -stash reduced
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design -import gold -as gold
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design -import reduced -as reduced
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miter -equiv -flatten -make_assert -make_outputs gold reduced miter
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sat -verify -prove-asserts -show-ports miter
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