mirror of https://github.com/YosysHQ/yosys.git
139 lines
3.6 KiB
Verilog
139 lines
3.6 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera Cyclone IV devices Input Buffer Primitive */
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module cycloneiv_io_ibuf
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(output o, input i, input ibar);
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assign ibar = ibar;
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assign o = i;
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endmodule // cycloneiv_io_ibuf
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/* Altera Cyclone IV devices Output Buffer Primitive */
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module cycloneiv_io_obuf
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(output o, input i, input oe);
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assign o = i;
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assign oe = oe;
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endmodule // cycloneiv_io_obuf
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/* Altera Cyclone IV LUT Primitive */
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module cycloneiv_lcell_comb
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(output combout, cout,
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input dataa, datab, datac, datad, cin);
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parameter lut_mask = 16'hFFFF;
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parameter dont_touch = "off";
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parameter lpm_type = "cycloneiv_lcell_comb";
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parameter sum_lutc_input = "datac";
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reg cout_tmp;
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reg combout_tmp;
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reg [1:0] isum_lutc_input;
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wire dataa_in;
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wire datab_in;
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wire datac_in;
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wire datad_in;
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wire cin_in;
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// Simulation model of 4-input LUT
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function lut4;
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input [15:0] mask;
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input dataa, datab, datac, datad;
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reg [7:0] s3;
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reg [3:0] s2;
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reg [1:0] s1;
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begin
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s3 = datad ? mask[15:8] : mask[7:0];
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s2 = datac ? s3[7:4] : s3[3:0];
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s1 = datab ? s2[3:2] : s2[1:0];
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lut4 = dataa ? s1[1] : s1[0];
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end
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endfunction // lut4
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initial
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begin
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if (sum_lutc_input == "datac")
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isum_lutc_input = 0;
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else if (sum_lutc_input == "cin")
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isum_lutc_input = 1;
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else
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begin
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$display ("Error: Invalid sum_lutc_input specified\n");
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$display ("Time: %0t Instance: %m", $time);
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isum_lutc_input = 2;
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end
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end
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always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
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begin
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if (isum_lutc_input == 0) // datac
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begin
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combout_tmp = lut4(lut_mask, dataa_in, datab_in,
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datac_in, datad_in);
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end
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else if (isum_lutc_input == 1) // cin
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begin
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combout_tmp = lut4(lut_mask, dataa_in, datab_in,
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cin_in, datad_in);
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end
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cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
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end
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and (combout, combout_tmp, 1'b1) ;
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and (cout, cout_tmp, 1'b1) ;
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endmodule // cycloneiv_lcell_comb
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/* Altera D Flip-Flop Primitive */
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module dffeas
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(output q,
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input d, clk, clrn, prn, ena,
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input asdata, aload, sclr, sload);
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// Timing simulation is not covered
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parameter power_up="dontcare";
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parameter is_wysiwyg="false";
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reg q_tmp;
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wire reset;
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reg [7:0] debug_net;
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assign reset = (prn && sclr && ~clrn && ena);
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assign q = q_tmp & 1'b1;
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always @(posedge clk, posedge aload) begin
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if(reset) q_tmp <= 0;
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else q_tmp <= d;
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end
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assign q = q_tmp;
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endmodule // dffeas
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