mirror of https://github.com/YosysHQ/yosys.git
16 lines
318 B
Plaintext
16 lines
318 B
Plaintext
read_verilog -sv <<EOT
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module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
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wire[8:0] a = 8'b0;
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initial begin
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a += i;
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a += j;
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end
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assign o = a;
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endmodule
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EOT
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proc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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