mirror of https://github.com/YosysHQ/yosys.git
16 lines
316 B
Plaintext
16 lines
316 B
Plaintext
read_verilog -sv <<EOT
|
|
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
|
|
wire[8:0] a = 8'b0;
|
|
initial begin
|
|
a |= i;
|
|
a |= j;
|
|
end
|
|
assign o = a;
|
|
endmodule
|
|
EOT
|
|
proc
|
|
equiv_opt -assert opt_expr -fine
|
|
design -load postopt
|
|
|
|
select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
|