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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 19:31:00 +02:00
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521663f09e8bc22f57a7c03476672b0b9718bc84
yosys/passes
T
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Clifford Wolf 521663f09e Add missing enable_undef to "sat -tempinduct-def", fixes #883
Signed-off-by: Clifford Wolf <[email protected]>
2019-05-02 00:03:31 +02:00
..
cmds
Fix floating point exception in qwp, fixes #923
2019-05-01 15:06:46 +02:00
equiv
Add -undef option to equiv_opt, passed to equiv_induct
2019-04-26 11:16:48 -07:00
fsm
fsm_opt: Fix runtime error for FSMs without a reset state
2019-02-07 10:35:36 +00:00
hierarchy
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
memory
memory_bram: Fix multiport make_transp
2019-04-07 16:56:31 +01:00
opt
Fix segfault in wreduce
2019-04-30 22:20:45 +02:00
pmgen
Misspelling
2019-04-25 16:46:13 -07:00
proc
Improve proc full_case detection and handling, fixes #931
2019-04-18 15:13:47 +02:00
sat
Add missing enable_undef to "sat -tempinduct-def", fixes #883
2019-05-02 00:03:31 +02:00
techmap
Merge pull request #914 from YosysHQ/xc7srl
2019-04-22 13:31:30 -07:00
tests
flowmap: implement depth relaxation.
2019-01-08 01:13:05 +00:00
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