luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 01:53:53 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
4ffdee65e034493cf1eafd9f94d770c88d2f35e0
yosys/tests/fmt
T
History
Charlotte 4ffdee65e0 cxxrtl: store comb $print cell last EN/ARGS in module 
statics were obviously wrong -- may be multiple instantiations of any
given module.  Extend test to cover this.
2023-08-11 04:46:52 +02:00
..
fuzz
fmt: merge fuzzers since we don't rely on BigInteger logic
2023-08-11 04:46:52 +02:00
.gitignore
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
always_comb_tb.cc
cxxrtl: store comb $print cell last EN/ARGS in module
2023-08-11 04:46:52 +02:00
always_comb_tb.v
cxxrtl: store comb $print cell last EN/ARGS in module
2023-08-11 04:46:52 +02:00
always_comb.v
cxxrtl: WIP: adjust comb display cells to only fire on change
2023-08-11 04:46:52 +02:00
always_display.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
always_full_tb.cc
tests: test cxxrtl against iverilog (and uncover bug!)
2023-08-11 04:46:52 +02:00
always_full_tb.v
tests: test cxxrtl against iverilog (and uncover bug!)
2023-08-11 04:46:52 +02:00
always_full.v
cxxrtl: WIP: adjust comb display cells to only fire on change
2023-08-11 04:46:52 +02:00
display_lm_tb.cc
fmt: rudimentary %m support (= %l)
2023-08-11 04:46:52 +02:00
display_lm.v
fmt: rudimentary %m support (= %l)
2023-08-11 04:46:52 +02:00
initial_display.v
fmt: format %t consistently at initial
2023-08-11 04:46:52 +02:00
roundtrip_tb.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
roundtrip.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
run-test.sh
cxxrtl: WIP: adjust comb display cells to only fire on change
2023-08-11 04:46:52 +02:00