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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 02:57:40 +02:00
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4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c
yosys/tests/techmap
T
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Clifford Wolf 4fd1a4c12b Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
2014-03-11 11:39:30 +01:00
..
.gitignore
Added tests/techmap/mem_simple_4x1
2014-02-21 12:06:40 +01:00
mem_simple_4x1_cells.v
Added tests/techmap/mem_simple_4x1
2014-02-21 12:06:40 +01:00
mem_simple_4x1_map.v
Use private namespace in mem_simple_4x1_map
2014-02-21 12:14:38 +01:00
mem_simple_4x1_runtest.sh
Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
2014-03-11 11:39:30 +01:00
mem_simple_4x1_tb.v
Added tests/techmap/mem_simple_4x1
2014-02-21 12:06:40 +01:00
mem_simple_4x1_uut.v
Added tests/techmap/mem_simple_4x1
2014-02-21 12:06:40 +01:00
run-test.sh
Added tests/techmap/mem_simple_4x1
2014-02-21 12:06:40 +01:00
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