Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 03:32:09 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
4fb9ccfcd81db6d2e574bea3d142b714126d1123
yosys/techlibs
T
History
Eddie Hung 4fb9ccfcd8 synth_ice40 to use renamed files
2019-04-17 12:22:03 -07:00
..
achronix
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
anlogic
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
common
synth to take -abc9 argument
2019-02-20 11:08:49 -08:00
coolrunner2
Unify usage of noflatten among architectures
2019-01-04 11:37:25 +01:00
easic
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
ecp5
ecp5: Demote conflicting FF init values to a warning
2019-03-04 11:26:20 +00:00
gowin
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
greenpak4
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
ice40
synth_ice40 to use renamed files
2019-04-17 12:22:03 -07:00
intel
Fixing issues in CycloneV cell sim
2019-04-11 19:59:03 -05:00
sf2
Add link to SF2 / igloo2 macro library guide
2019-03-07 09:08:26 -08:00
xilinx
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
Powered by Gitea Version: 1.27.2 Page: 2824ms Template: 495ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API