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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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4f4e70876f06738fa7dda24e01ac296fe318264a
yosys/frontends/verilog
T
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Zachary Snow 4f4e70876f sv: allow typenames as function return types
2021-03-19 12:08:43 -04:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
Makefile.inc
Treat all bison warnings as errors in verilog front-end
2020-07-15 11:57:31 +02:00
preproc.cc
verilog: fix handling of nested ifdef directives
2021-03-01 12:28:33 -05:00
preproc.h
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
verilog_frontend.cc
verilog: rebuild user_type_stack from globals before parsing file
2021-03-18 20:52:36 -04:00
verilog_frontend.h
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
verilog_lexer.l
sv: extended support for integer types
2021-02-28 16:31:56 -05:00
verilog_parser.y
sv: allow typenames as function return types
2021-03-19 12:08:43 -04:00
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