Eddie Hung b3378745fd Revert "Recognise default entry in case even if all cases covered (fix for #931)"

2019-04-15 17:52:45 -07:00

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aiger

Support and differentiate between ASCII and binary AIG testing

2019-02-08 12:41:59 -08:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

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errors

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fsm

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hana

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liberty

Liberty file parser now accepts superfluous ;

2019-03-27 15:16:19 +01:00

lut

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

memories

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opt

Fix WREDUCE on FF not fixing ARST_VALUE parameter.

2019-02-22 10:30:42 -08:00

realmath

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sat

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share

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simple

fix local name resolution in prefix constructs

2019-03-18 20:43:20 -04:00

smv

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sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Add missing .gitignore

2018-12-06 07:29:37 +01:00

techmap

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tools

Merge https://github.com/YosysHQ/yosys into read_aiger

2019-03-19 08:52:31 -07:00

unit

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various

Revert "Recognise default entry in case even if all cases covered (fix for #931)"

2019-04-15 17:52:45 -07:00

vloghtb

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