Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

2014-07-23 09:52:55 +02:00

..

autotest

SigSpec refactoring: using the accessor functions everywhere

2014-07-22 20:39:37 +02:00

blif

Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

2014-07-23 09:52:55 +02:00

btor

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

2014-07-22 20:58:44 +02:00

edif

Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

2014-07-23 09:52:55 +02:00

ilang

SigSpec refactoring: using the accessor functions everywhere

2014-07-22 20:39:37 +02:00

intersynth

SigSpec refactoring: using the accessor functions everywhere

2014-07-22 20:39:37 +02:00

spice

SigSpec refactoring: using the accessor functions everywhere

2014-07-22 20:39:37 +02:00

verilog

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

2014-07-22 20:58:44 +02:00