Dhaval 4de892fbe4 Merge 829a2f174a into cede13a742		2026-04-02 11:20:15 -05:00
..
aiger	yosys: use newcelltypes for yosys_celltypes users	2026-03-04 12:39:44 +01:00
aiger2	Enable xaiger2 pass when not in NDEBUG	2025-11-21 14:23:32 -08:00
ast	genrtlil: even faster removeSignalFromCaseTree	2026-03-18 23:33:35 +01:00
blif	blifparse: add bounds check	2026-02-11 12:16:02 +01:00
json	Support param. default values in JSON FE and SV BE	2026-02-11 08:10:55 -08:00
liberty	read_liberty: support loopy retention cells	2025-11-20 13:21:32 +01:00
rpc	Remove .c_str() from parameters to log_debug()	2025-09-23 19:10:33 +12:00
rtlil	Work around `std::reverse` miscompilation with empty range	2026-03-06 02:03:21 +00:00
verific	Merge 829a2f174a into cede13a742	2026-04-02 11:20:15 -05:00
verilog	support automatic lifetime qualifier on procedural variables	2026-02-27 20:42:52 +03:00