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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-08 02:52:53 +02:00
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4de3ee093eecf4e766734fddb113187df36be31a
yosys/passes
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History
Robert O'Callahan 4de3ee093e Mark kept FF output wires as ports directly instead of via the 'keep' attribute
2025-08-14 22:26:38 +00:00
..
cmds
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-08-11 13:34:10 +02:00
equiv
equiv_simple: Avoid std::array
2025-08-08 12:37:38 +12:00
fsm
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
hierarchy
Reapply "Add groups to command reference"
2025-08-06 13:52:12 +12:00
memory
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-08-11 13:34:10 +02:00
opt
Reapply "Add groups to command reference"
2025-08-06 13:52:12 +12:00
pmgen
Reapply "Add groups to command reference"
2025-08-06 13:52:12 +12:00
proc
Proc: Use selections consistently
2025-05-31 12:04:42 +12:00
sat
Reapply "Add groups to command reference"
2025-08-06 13:52:12 +12:00
techmap
Mark kept FF output wires as ports directly instead of via the 'keep' attribute
2025-08-14 22:26:38 +00:00
tests
test_cell: Add comment on $pmux
2025-08-12 10:57:59 +12:00
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