yosys/backends/verilog
Jakub Janeczko ca75829c33
new transparent memory verilog pattern
2026-07-23 01:53:54 +02:00
..
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
verilog_backend.cc new transparent memory verilog pattern 2026-07-23 01:53:54 +02:00
verilog_backend.h verilog backend: runtime optimization for keyword pool 2026-05-29 17:53:31 +00:00