Clifford Wolf 4d37710e82 Merge pull request #1281 from mmicko/efinix ...

Initial support for Efinix Trion series FPGAs

2019-08-22 18:06:02 +02:00

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achronix

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

anlogic

anlogic : Fix alu mapping

2019-08-03 14:47:33 +02:00

common

Missing newline

2019-08-20 20:37:52 -07:00

coolrunner2

Fix spacing

2019-08-06 16:47:55 -07:00

easic

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ecp5

Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro

2019-08-19 09:56:17 -07:00

efinix

Fix formating

2019-08-11 17:05:24 +02:00

gowin

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

greenpak4

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ice40

Merge pull request #1304 from YosysHQ/eddie/abc9_refactor

2019-08-20 11:59:31 -07:00

intel

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

sf2

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

xilinx

Merge pull request #1209 from YosysHQ/eddie/synth_xilinx

2019-08-20 12:55:26 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00