mirror of https://github.com/YosysHQ/yosys.git
51 lines
1.6 KiB
Verilog
51 lines
1.6 KiB
Verilog
module top(
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a, b, x,
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o1_1, o1_2, o1_3, o1_4,
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o2_1, o2_2, o2_3, o2_4,
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o3_1, o3_2, o3_3, o3_4,
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o4_1, o4_2, o4_3, o4_4,
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o5_1, o5_2, o5_3, o5_4
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);
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input [3:0] a;
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input b;
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input [7:0] x;
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output o1_1, o1_2, o1_3, o1_4;
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output o2_1, o2_2, o2_3, o2_4;
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output o3_1, o3_2, o3_3, o3_4;
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output o4_1, o4_2, o4_3, o4_4;
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output o5_1, o5_2, o5_3, o5_4;
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// RHS = {b, 4'b0000}: same width as `a`, lower bits zero.
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assign o1_1 = a < {b, 4'b0000};
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assign o1_2 = a >= {b, 4'b0000};
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assign o1_3 = {b, 4'b0000} > a;
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assign o1_4 = {b, 4'b0000} <= a;
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// RHS = {b, 5'b00000}: wider than `a`; `a` zero-extends to fit.
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assign o2_1 = a < {b, 5'b00000};
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assign o2_2 = a >= {b, 5'b00000};
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assign o2_3 = {b, 5'b00000} > a;
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assign o2_4 = {b, 5'b00000} <= a;
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// LHS = {1'b0, a}: explicit zero-extend on the bounded operand.
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assign o3_1 = {1'b0, a} < {b, 4'b0000};
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assign o3_2 = {1'b0, a} >= {b, 4'b0000};
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assign o3_3 = {b, 4'b0000} > {1'b0, a};
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assign o3_4 = {b, 4'b0000} <= {1'b0, a};
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// Lowered form of `(signed x < -1)` after sign-stripping:
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// A = {1'b1, x[N-2:0]}, B = {x[N-1], (N-1)'b1}, both unsigned.
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// Expected: Y = x[N-1] && ~&x[N-2:0]
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assign o4_1 = {1'b1, x[6:0]} < {x[7], 7'b1111111};
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assign o4_2 = {1'b1, x[6:0]} >= {x[7], 7'b1111111};
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assign o4_3 = {x[7], 7'b1111111} > {1'b1, x[6:0]};
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assign o4_4 = {x[7], 7'b1111111} <= {1'b1, x[6:0]};
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// Same pattern at width = 2 (smallest viable N).
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assign o5_1 = {1'b1, x[0]} < {x[1], 1'b1};
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assign o5_2 = {1'b1, x[0]} >= {x[1], 1'b1};
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assign o5_3 = {x[1], 1'b1} > {1'b1, x[0]};
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assign o5_4 = {x[1], 1'b1} <= {1'b1, x[0]};
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endmodule
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