mirror of https://github.com/YosysHQ/yosys.git
82 lines
1.7 KiB
Plaintext
82 lines
1.7 KiB
Plaintext
# Equivalence tests using narrow operands
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read_verilog equiv_narrow.v
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hierarchy -top equiv_add3
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_add3"
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read_verilog equiv_narrow.v
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hierarchy -top equiv_add4
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_add4"
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read_verilog equiv_narrow.v
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hierarchy -top equiv_add5
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_add5"
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read_verilog equiv_narrow.v
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hierarchy -top equiv_add8
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_add8: ok"
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read_verilog equiv_narrow.v
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hierarchy -top equiv_signed
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_signed: ok"
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read_verilog equiv_narrow.v
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hierarchy -top equiv_mixed_w
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_mixed_w: ok"
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read_verilog equiv_narrow.v
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hierarchy -top equiv_repeated
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_repeated: ok"
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read_verilog equiv_narrow.v
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hierarchy -top equiv_1bit_wide
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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log "equiv_1bit_wide: ok"
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