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4cdba00e25d892b90c0ee48716c17dec60e472db
yosys/techlibs/xilinx
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Eddie Hung 4cdba00e25 FDCE ports to be alphabetical
2019-12-31 15:24:02 -08:00
..
tests
xilinx: Test our DSP48A/DSP48A1 simulation models.
2019-12-23 20:36:43 +01:00
.gitignore
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
abc9_map.v
Fix incorrect $__ABC9_ASYNC[01] box
2019-12-31 11:13:50 -08:00
abc9_model.v
Fix attributes on $__ABC9_ASYNC[01] whitebox
2019-12-31 11:14:11 -08:00
abc9_unmap.v
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
2019-12-19 11:23:41 -08:00
abc9_xc7_nowide.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_xc7.box
Do not offset FD* box timings due to -46ps Tsu
2019-12-30 14:35:10 -08:00
abc9_xc7.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
arith_map.v
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
cells_sim.v
FDCE ports to be alphabetical
2019-12-31 15:24:02 -08:00
cells_xtra.py
xilinx: Add simulation models for remaining CLB primitives.
2019-12-19 18:04:04 +01:00
cells_xtra.v
xilinx: Add simulation models for remaining CLB primitives.
2019-12-19 18:04:04 +01:00
lut_map.v
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
lutrams_map.v
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
2019-12-16 12:06:47 -08:00
lutrams.txt
Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
2019-12-16 10:41:13 -08:00
Makefile.inc
xilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 13:43:43 +01:00
mux_map.v
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
synth_xilinx.cc
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
xc3s_mult_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc3sda_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc6s_brams_map.v
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
xc6s_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc6s_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc6s_ff_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
xc7_brams_map.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc7_ff_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
xc7_xcu_brams.txt
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
xcu_brams_map.v
xilinx: Add support for UltraScale[+] BRAM mapping
2019-10-23 11:47:37 +01:00
xcu_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xcup_urams_map.v
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xcup_urams.txt
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xilinx_dffopt.cc
xilinx_dffopt: Keep order of LUT inputs.
2019-12-19 18:01:43 +01:00