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aiger
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switch argument order to work with macOS getopt
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2020-09-23 12:48:26 +02:00 |
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arch
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quicklogic: Add .gitignore file for test outputs.
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2021-03-23 17:35:00 +01:00 |
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asicworld
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…
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bram
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tests/bram: Do not generate write address collisions.
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2021-03-08 16:53:03 +01:00 |
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errors
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…
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fsm
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tests: fsm to use a randomly-generated seed
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2020-04-24 14:31:33 -07:00 |
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hana
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…
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liberty
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dfflibmap: Refactor to use dfflegalize internally.
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2020-07-09 18:51:03 +02:00 |
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lut
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…
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memfile
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Added 'set -e' into tests/memfile/run-test.sh
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2020-02-06 10:45:40 -03:00 |
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memories
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tests: Parallelize
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2020-09-21 15:07:02 +02:00 |
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opt
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opt_clean: Remove init attribute bits together with removed DFFs.
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2021-03-15 17:16:53 +01:00 |
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opt_share
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tests: Parallelize
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2020-09-21 15:07:02 +02:00 |
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proc
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proc_arst: Add special-casing of clock signal in conditionals.
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2021-03-15 17:17:29 +01:00 |
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realmath
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…
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rpc
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rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
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2020-03-06 15:29:01 +01:00 |
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sat
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assertpmux: Fix crash on unused $pmux output.
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2021-02-22 23:30:28 +01:00 |
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select
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Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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2020-04-22 15:35:05 -07:00 |
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share
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…
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simple
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verilog: fix buf/not primitives with multiple outputs
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2021-03-17 11:44:03 -04:00 |
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simple_abc9
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Set aside extraneous tests in simple_abc9 test suite
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2021-03-01 12:13:11 -05:00 |
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smv
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…
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sva
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…
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svinterfaces
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…
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svtypes
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verilog: check entire user type stack for type definition
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2021-03-21 19:35:13 -04:00 |
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techmap
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Add tests for some common techmap files.
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2021-02-24 01:07:34 +01:00 |
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tools
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memory_dff: Remove now-useless write port handling.
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2021-03-08 20:16:29 +01:00 |
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unit
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…
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various
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blackbox: Include whiteboxed modules
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2021-03-17 13:58:04 +00:00 |
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verilog
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sv: allow typenames as function return types
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2021-03-19 12:08:43 -04:00 |
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vloghtb
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…
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gen-tests-makefile.sh
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tests: Parallelize
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2020-09-21 15:07:02 +02:00 |
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