mirror of https://github.com/YosysHQ/yosys.git
32 lines
501 B
Plaintext
32 lines
501 B
Plaintext
# base case is able to map
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read_verilog << EOF
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module and_x3 (
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input a, b, c, d,
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output reg y
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);
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assign y = (a&b)&(c&d);
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endmodule
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EOF
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hierarchy -top and_x3
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opt
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extract -map ./bug3515.v
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select -assert-count 1 t:mod_74x08_3
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# more needles than haystacks; not able to map
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design -reset
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read_verilog << EOF
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module mod_and_or (
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input a, b, c, d,
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output reg y
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);
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assign y = (a&b)|(c&d);
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endmodule
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EOF
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hierarchy -top mod_and_or
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opt
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extract -map ./bug3515.v
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select -assert-count 2 t:$and
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