yosys/tests/liberty/dff.lib.verilogsim.ok

module dff (D, CLK, Q);
  reg IQ, IQN;
  input D;
  input CLK;
  output Q;
  assign Q = IQ; // IQ
  always @(posedge CLK) begin
      IQ <= D;
  end
  always @(posedge CLK) begin
      IQN <= ~(D);
  end
endmodule