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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-07 10:32:59 +02:00
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4bc4e4eb41ee8de4ea4b8cb2f12bcdd0c8093504
yosys/tests/arch/quicklogic
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Emil J. Tywoniak ae281720cf tests: remove unstable FPGA synthesis result checks
2025-11-12 11:52:04 +01:00
..
pp3
tests: remove unstable FPGA synthesis result checks
2025-11-12 11:52:04 +01:00
qlf_k6n10f
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
.gitignore
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
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