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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 04:19:56 +02:00
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4a3669d871dccf7ff772ad584b9f1271f75e4eb5
yosys/techlibs/common
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History
Clifford Wolf 0836a1f2ba Bugfix in dffsr techmap rules
2013-10-18 13:24:44 +02:00
..
blackbox.sed
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
Makefile.inc
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
simlib.v
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
stdcells_sim.v
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00
stdcells.v
Bugfix in dffsr techmap rules
2013-10-18 13:24:44 +02:00
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