mirror of https://github.com/YosysHQ/yosys.git
24 lines
460 B
Systemverilog
24 lines
460 B
Systemverilog
module opt_compact_prefix_multi_match (
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input logic [7:0] sig,
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output logic [7:0] sig2
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);
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always_comb begin
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sig2 = '0;
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for (int I = 0, indx = 0; I < 8; I++) begin
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if (sig[I]) begin
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sig2[indx] = sig[I];
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indx += 1;
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end
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end
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end
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endmodule
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module opt_compact_prefix_multi_keep (
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input logic sel,
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input logic [7:0] a,
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input logic [7:0] b,
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output logic [7:0] y
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);
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assign y = sel ? a : b;
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endmodule
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