mirror of https://github.com/YosysHQ/yosys.git
155 lines
3.0 KiB
Plaintext
155 lines
3.0 KiB
Plaintext
log -header "Positive case: (a + ~b) + 1 => a - b => a + (-b)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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assign y = (a + ~b) + 1;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$not
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Unsigned positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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assign y = (a + ~b) + 1;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$not
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Positive case B: 1 + (a + ~b) => a - b => a + (-b)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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assign y = 1 + (a + ~b);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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select -assert-none t:$not
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Anchor case: output wider than operands"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [11:0] y;
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assign y = (a + ~b) + 1;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-count 1 t:$neg
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: fanout on inner add output"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y, z);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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output wire [7:0] z;
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(* keep *) wire [7:0] s;
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assign s = a + ~b;
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assign y = s + 1;
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assign z = s + a;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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# Should NOT transform due to fanout on inner add output (marked with keep)
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select -assert-count 3 t:$add
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select -assert-count 1 t:$not
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select -assert-none t:$sub
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select -assert-none t:$neg
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design -reset
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log -pop
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log -header "Negative case: mixed signedness on inner add"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire [7:0] b;
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output wire signed [7:0] y;
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assign y = (a + ~b) + 1;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-none t:$sub
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design -reset
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log -pop
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log -header "Negative case: ~b not directly on inner add input"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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wire [7:0] nb;
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assign nb = ~b;
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assign y = (a + (nb ^ 8'h00)) + 1;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-none t:$sub
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design -reset
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log -pop
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