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24 lines
676 B
Plaintext
24 lines
676 B
Plaintext
# Clock domain mismatch — gold has two clocks, gate has one.
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# The pass should error declaring inequivalence.
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design -reset
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read_verilog <<EOF
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module gold(input clk1, input clk2,
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input [7:0] a, b, c, d,
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output reg [7:0] q1, q2);
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always @(posedge clk1) q1 <= a + b;
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always @(posedge clk2) q2 <= c + d;
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endmodule
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module gate(input clk1, input clk2,
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input [7:0] a, b, c, d,
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output reg [7:0] q1, q2);
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always @(posedge clk1) begin
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q1 <= a + b;
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q2 <= c + d;
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end
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endmodule
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EOF
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proc; opt_clean
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logger -expect error "Designs are inequivalent: clock domain count mismatch" 1
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cone_partition -v gold gate
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