Jannis Harder 4bb4b6c662 verific: Extend -sva-continue-on-err to handle FSM explosion ...

This also rolls back any added cells and wires, since we might have
added a lot of helper logic by the point we detect this.

2025-09-27 21:13:02 +02:00

..

aiger

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

aiger2

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

ast

verilog: Bufnorm cell backend and frontend support

2025-09-17 14:01:09 +02:00

blif

Update frontends to avoid bits()

2025-09-16 03:17:23 +00:00

json

Use fast path for 32-bit Const integer constructor in more places

2025-09-16 03:17:24 +00:00

liberty

Remove .c_str() calls from parameters to log_header()

2025-09-16 23:00:42 +00:00

rpc

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

rtlil

Use fast path for 32-bit Const integer constructor in more places

2025-09-16 03:17:24 +00:00

verific

verific: Extend -sva-continue-on-err to handle FSM explosion

2025-09-27 21:13:02 +02:00

verilog

Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort

2025-09-22 11:14:39 +02:00