mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-04 19:31:00 +02:00
18 lines
324 B
Plaintext
18 lines
324 B
Plaintext
# pitfall
|
|
read_verilog cmos.v
|
|
prep -top cmos_demo
|
|
techmap
|
|
abc -liberty ../intro/mycells.lib;;
|
|
show -format dot -prefix cmos_00
|
|
|
|
# reset
|
|
design -reset
|
|
|
|
# fixed output
|
|
read_verilog cmos.v
|
|
prep -top cmos_demo
|
|
techmap
|
|
splitnets -ports
|
|
abc -liberty ../intro/mycells.lib;;
|
|
show -lib ../intro/mycells.v -format dot -prefix cmos_01
|