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.gitignore
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aes_kexp128.v
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always01.v
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always02.v
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always03.v
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arraycells.v
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arrays01.v
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arrays02.sv
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Add proper test for SV-style arrays
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2019-06-20 12:06:07 +02:00 |
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attrib01_module.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib02_port_decl.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib03_parameter.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib04_net_var.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib05_port_conn.v.DISABLED
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib06_operator_suffix.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib07_func_call.v.DISABLED
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib08_mod_inst.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib09_case.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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carryadd.v
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const_branch_finish.v
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Propagate const_fold through generate blocks and branches
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2020-08-09 17:21:08 -04:00 |
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constmuldivmod.v
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Expand tests/simple/constmuldivmod.v
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2020-05-28 22:59:04 +02:00 |
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constpower.v
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defvalue.sv
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Add defvalue test, minor autotest fixes for .sv files
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2019-06-19 12:12:08 +02:00 |
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dff_different_styles.v
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dff_init.v
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dynslice.v
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Add dynamic slicing Verilog testcase
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2020-03-31 11:51:31 -07:00 |
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fiedler-cooley.v
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forgen01.v
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forgen02.v
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forloops.v
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fsm.v
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generate.v
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Module name scope support
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2020-08-20 20:15:08 -04:00 |
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graphtest.v
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hierarchy.v
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hierdefparam.v
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i2c_master_tests.v
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implicit_ports.v
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Rename implicit_ports.sv test to implicit_ports.v
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2019-06-07 13:12:25 +02:00 |
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localparam_attr.v
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loops.v
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macros.v
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mem2reg.v
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mem_arst.v
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Make SV2017 compliant courtesy of @wsnyder
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2019-12-12 07:34:07 -08:00 |
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memory.v
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multiplier.v
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muxtree.v
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omsp_dbg_uart.v
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operators.v
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param_attr.v
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paramods.v
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partsel.v
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Bugfix in partsel.v signed indices test cases
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2020-05-02 11:21:01 +02:00 |
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process.v
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realexpr.v
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Add test case for real parameters
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2019-08-20 11:38:21 +02:00 |
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repwhile.v
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retime.v
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rotate.v
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run-test.sh
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tests/simple: remove "nullglob" shopt
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2020-09-21 15:07:02 +02:00 |
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scopes.v
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signedexpr.v
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sincos.v
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specify.v
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string_format.v
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Allow %0s $display format specifier
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2020-08-09 17:19:49 -04:00 |
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subbytes.v
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task_func.v
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undef_eqx_nex.v
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usb_phy_tests.v
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values.v
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vloghammer.v
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wandwor.v
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wreduce.v
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xfirrtl
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
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2019-07-31 09:27:38 -07:00 |
