Michael Christensen 67d6f3973b Fix use of blif name in synth_xilinx command

2021-04-27 02:29:52 -07:00

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achronix

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

anlogic

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

common

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

coolrunner2

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

easic

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

ecp5

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

efinix

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

gowin

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

greenpak4

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

ice40

Add default assignments to other SB_* simulation models

2021-04-20 18:52:36 +02:00

intel

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

intel_alm

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

machxo2

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

nexus

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

quicklogic

quicklogic: ABC9 synthesis

2021-04-17 20:54:58 +02:00

sf2

sf2: fix name of AND modules

2021-04-09 16:46:05 +02:00

xilinx

Fix use of blif name in synth_xilinx command

2021-04-27 02:29:52 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00