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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 12:44:23 +02:00
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442a8e2875eab679ed3b31aee3d9725b87dbf4fc
yosys/frontends
T
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Clifford Wolf 442a8e2875 Implemented basic real arithmetic
2014-06-14 08:51:22 +02:00
..
ast
Implemented basic real arithmetic
2014-06-14 08:51:22 +02:00
ilang
Fixed clang -Wdeprecated-register warnings
2014-04-20 14:28:23 +02:00
liberty
new flags -ignore_miss_func and -ignore_miss_dir for read_liberty
2014-05-28 16:50:13 +02:00
verific
Fixed mapping of Verific WIDE_DFFRS operator
2014-03-20 13:40:01 +01:00
verilog
Added Verilog lexer and parser support for real values
2014-06-13 11:29:23 +02:00
vhdl2verilog
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
2014-03-11 14:24:24 +01:00
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